This invention relates to integrated circuits, and more particularly to a high-voltage differential input receiver.
The voltage supplied to integrated circuits on a chip has decreased, for example, from 3.3 volts to 2.5 volts to 1.8 volts to 1.2 volts, as the integration processes have advanced. It is not uncommon that the voltage supplied to power the components on the chip is lower than the voltage levels used on the bus or in other circuits with which the chip communicates. For example, the Rambus Signal Level (RSL) of a Rambus Channel is typically between 1.0 volts and 1.8 volts, while the voltage supply on an exemplary chip that communicates with the Rambus Channel may be 1.2 volts.
As integrated circuit processes have advanced, the size of integrated circuits has decreased and the thickness of layers in the integrated circuits has been dramatically reduced. The oxide layers that form the gates of n-channel and p-channel transistors in the integrated circuits are consequently made thinner, and are susceptible to electrical overstress (EOS) when the voltage between the gate and the source, and also the voltage between the gate and the drain exceeds a maximum safe magnitude.
Increasingly, the circuitry on a chip must interface with voltage swing levels that are higher than the core voltage used to power the circuitry on the chip. The likelihood of electrical overstress of the gate oxide layers in the circuitry is therefore increasingly problematic. With regard to transistors on the chip, particularly those that interface with higher voltage levels off the chip, the voltage between the gate and the drain and the voltage between the gate and the source ought to be kept below a predetermined safe magnitude without sacrificing performance or consuming more power.